This invention relates to semiconductor technology and, in particular, to field-effect transistors (xe2x80x9cFETsxe2x80x9d) of the insulated-gate type. All of the insulated-gate FETs (xe2x80x9cIGFETsxe2x80x9d) described below are surface-channel enhancement-mode IGFETs except as otherwise indicated.
An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone that extends between a source and a drain in a semiconductor body. The channel zone in an-enhancement-mode IGFET is part of a body region, commonly termed the substrate or substrate region, that forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all the semiconductor body material situated between the source and drain. During operation of an enhancement-mode IGFET, charge carriers move from the source to the drain through a channel induced in the channel zone along the upper semiconductor surface. The channel length is the distance between the source and drain along the upper semiconductor surface.
Over the last forty years, the minimum value of IGFET channel length has decreased generally in the manner prescribed by Moore, xe2x80x9cProgress in Digital Integrated Electronics,xe2x80x9d Tech. Dig., 1975 Int""l Elec. Devs. Meeting, 1-3 Dec. 1975, pages 11-13. Per Moore""s xe2x80x9clawxe2x80x9d, the minimum channel length decreases roughly in proportion to a factor of 1/{square root over (2)} (approximately 0.7) every three years. IGFETs employed in state-of-the-art integrated circuits (xe2x80x9cICsxe2x80x9d) manufactured at volume-production quantities today have minimum channel lengths considerably less than 1 xcexcm, typically 0.25 xcexcm and moving towards 0.18 xcexcm. The minimum channel length for volume-production ICs is expected to be roughly 0.1 xcexcm in eight to ten years.
An IGFET that behaves generally in the way prescribed by the classical model for an IGFET is often characterized as a xe2x80x9clong-channelxe2x80x9d device. An IGFET is described as a xe2x80x9cshort-channelxe2x80x9d device when the channel length is shortened to such an extent that the IGFET""s behavior deviates significantly from the behavior of the classical IGFET model. Both short-channel and long-channel IGFETs are variously employed in ICs. Because drive current generally increases with decreasing channel length, the great majority of IGFETs used in very large scale integration applications are laid out to have as small a channel length as can be reliably produced with the available lithographic technology.
One short-channel effect is roll-off of the threshold voltage. See (a) Yau, xe2x80x9cA Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET""sxe2x80x9d, Solid-State Electronics, October 1974, pages 1059-1069, and (b) Liu et al, xe2x80x9cThreshold Voltage Model for Deep-Submicrometer MOSFET""sxe2x80x9d, IEEE Trans. Elec. Devs., Vol. 40, No. 1, January 1993, pages 86-95. The threshold voltage is the value of gate-to-source voltage at which an IGFET switches between its on and off states for given definitions of the on and off states.
FIG. 1 illustrates a typical example of how threshold voltage VT rolls off for a conventional n-channel enhancement-mode IGFET whose parameters, other than channel length L, are fixed. As FIG. 1 indicates, threshold voltage VT has relatively little variation in the long-channel regime where channel length L is greater than transition value LX approximately equal to 0.4 xcexcm here. When channel length L drops below LX, the IGFET enters the short-channel regime in which threshold voltage VT rolls off sharply to zero.
In designing IGFETs with increasingly reduced channel length, an important trade-off is between drive current and leakage current. The drive current, preferably high, is the current that flows between the source and drain when the IGFET is turned fully on. The leakage current, preferably low, is the current that flows between the source and drain when the IGFET is turned off with the gate electrode electrically shorted to the source. Decreasing the channel length typically leads to an increase in the drive current. However, the leakage current also typically increases when the channel length is reduced.
Due to the foregoing trade-off, a short-channel IGFET is typically designed so that channel length L is of a value close to where threshold voltage VT starts to roil off sharply to zero. An L value of 0.25 xcexcm satisfies this requirement in FIG. 1. The resulting VT value of slightly more than 0.5 V is sufficiently high to enable a 0.25-xcexcm n-channel IGFET to switch reliably between its on and off states. However, threshold voltage VT for an n-channel IGFET having an L value of 0.10 xcexcm, as occurs in the next generation of IGFETs, is approximately 0.2 V. This is too low to be able to reliably turn such a 0.18-xcexcm IGFET off at zero gate-to-source voltage, especially in light of typical manufacturing variations.
The scaling principles developed by Dennard et al, xe2x80x9cDesign of Ion-Implanted MOSFET""s with Very Small Physical Dimensionsxe2x80x9d IEEE J. Solid-State Circs., Vol. SC-9, No. 5, October 1974, pages 256-268, have been utilized in downsizing IGFETS. In brief, Dennard et al specifies that IGFET dimensions are to be reduced approximately in proportion to a given scaling factor as the average net dopant concentration in the channel zone, i.e., the semiconductor body material situated between the source and drain in an enhancement-mode IGFET, is increased by the scaling factor. The voltages across various parts of the reduced-dimension IGFET are also generally to be reduced in proportion to the scaling factor.
The scaling theory of Dennard et al functions relatively well down to channel length in the vicinity of 1 xcexcm. Unfortunately, certain scaling limitations are encountered when the channel length is reduced significantly below 1 xcexcm. For example, electron tunneling effects preclude reducing the gate dielectric thickness to the value prescribed by the scaling theory.
Also, when the threshold voltage is to be adjusted by simply implanting the channel zone with ions of the same conductivity type as the channel zone, it is typically preferable that the threshold adjust implant be distinguishable from the vertical dopant profile in the bulk of the channel zone. In scaling an IGFET to channel length significantly less than 1 xcexcm according to the theory of Dennard et al, the threshold adjust implant merges inseparably into the vertical dopant profile in the bulk of the channel zone, thereby simply raising the average net dopant concentration in the channel zone by an approximately fixed amount that is largely independent of channel length. Attempting to extend the scaling theory to channel length significantly less than 1 xcexcm does not work well.
Various techniques have been utilized to improve the performance of IGFETs, including those operating in the short-channel regime, as IGFET dimensions are reduced. One performance-improvement technique involves providing an IGFET with a two-part drain for reducing hot carrier injection. FIG. 2 illustrates such a conventional n-channel enhancement-mode IGFET 10 created from a monocrystalline silicon semiconductor body having region 12 of lightly doped p-type body material. IGFET 10 has n-type source 14, n-type drain 16, intervening p-type channel zone 18, gate electrode 20, gate dielectric layer 22, and gate sidewall spacers 24 and 26. Drain 16 consists of heavily doped main portion 16M and more lightly doped extension 16E. Source 14 similarly consists of heavily doped main portion 14M and more lightly doped extension 14E. When IGFET 10 is turned on, electrons travel from source 14 to drain 16 by way of a thin channel induced in channel zone 18 along the upper semiconductor surface.
A pair of depletion regions extend respectively along the drain/body and source/body junctions. Under certain conditions, especially when the channel length is small, the drain depletion region can extend laterally to the source depletion region and merge with it below the upper semiconductor surface. This phenomenon is termed punchthrough. If the drain depletion region punches through to the source depletion region, the operation of the IGFET cannot be controlled with the gate electrode. Accordingly, punchthrough normally needs to be avoided.
One conventional technique for inhibiting punchthrough as channel length is reduced, and also for shifting threshold voltage roll-off to shorter channel length, is to increase the dopant concentration of the channel zone in a pocket portion along the source. See Ogura et al, xe2x80x9cA Half Micron MOSFET Using Double Implanted LDD,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, 11-15 Dec. 1982, pages 718-721. As an artifact of creating the increased-concentration pocket portion along the source, the dopant concentration in the channel zone is commonly increased in a corresponding pocket portion along the drain. Per Codella et al, xe2x80x9cHalo Doping Effects in Submicron DI-LDD Device Design,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, 1-4 Dec. 1985, pages 230-233, the pocket portions are commonly referred to as xe2x80x9chaloxe2x80x9d.
Increasing the dopant concentration in a halo pocket along the source reduces the thickness of the channel-zone part of the source depletion region, thereby deferring the onset of punchthrough. As the channel length is reduced, the halo pockets along the source and drain get closer together so as to increase the average net dopant concentration in the channel zone. This causes the threshold voltage to increase, thereby partially counteracting threshold voltage roll-off at short channel length.
FIG. 3 depicts a conventional n-channel enhancement-mode halo IGFET 30 as configured in Ogura et al or Codella et al. Except as described below, IGFET 30 contains the same regions as IGFET 10 in FIG. 2. As shown in FIG. 3, channel zone 18 in n-channel IGFET 30 includes a pair of p-type halo pocket portions 31 and 32 doped more heavily than the remainder of channel zone 18. Halo pockets 31 and 32 are situated along the inner boundaries of source 14 and drain 16 so as to inhibit punchthrough. Metal silicide layers 33, 34, and 35 respectively contact main source portion 14M, main drain portion 16M, and gate electrode 20.
Halo pockets 31 and 32 can be created in various ways. For example, p-type halo dopant is typically ion implanted through the upper semiconductor surface into the semiconductor body using gate electrode 20 as an implantation shield. The halo implant can be performed roughly perpendicular to the upper semiconductor surface as indicated in Ogura et al.
The halo implant can also be performed at a substantial angle to a perpendicular to the upper semiconductor surface. In this regard, see (a) Su, xe2x80x9cTilt Angle Effect on Optimizing HALO PMOS Performance,xe2x80x9d 1997 Int""l Conf. Simulation Semicon. Procs. and Devs., 8-10 Sep. 1997, pages 33-36, (b) Rodder et al, xe2x80x9cA Sub-0.18 xcexcm Gate Length CMOS Technology for High Performance (1.5 V) and Low Power (1.0 V),xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, 8-11 Dec. 1996, pages 563-566, (c) Hori, xe2x80x9cA 0.1-xcexcm CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS),xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, 11-14 Dec. 1994, pages 75-78, and (d) Hwang et al, xe2x80x9cDegradation of MOSFETs Drive Current Due to Halo Ion Implantation,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting, 8-11 Dec. 1996, pages 567-570.
The threshold voltage of n-channel IGFET 30 is adjusted by introducing p-type dopant, typically boron, into a portion 36 of channel zone 18. The threshold adjust dopant typically has a retrograde dopant concentration profile in that the maximum concentration of the threshold adjust dopant occurs below the upper semiconductor surface. The maximum concentration of the threshold adjust dopant may occur in, or below, a depletion region that extends across channel zone 18 along the upper semiconductor surface during IGFET operation. For example, the information presented in Ogura et al indicates that the maximum concentration of the threshold adjust dopant in Ogura et al occurs in the surface depletion region slightly more than 0.1 xcexcm below the upper semiconductor surface. As a result, the magnitude of the threshold voltage adjustment in Ogura et al is determined primarily by the dosage of the p-type dopant.
Shahidi et al, xe2x80x9cHigh Performance Devices for a 0.15 xcexcm CMOS Technology,xe2x80x9d IEEE Elect. Dev. Lett., Vol. 14, No. 10, October 1993, pages 466-468, and Taur et al, xe2x80x9cHigh Performance 0.1 xcexcm CMOS Devices with 1.5 V Power Supply,xe2x80x9d IEDM Tech. Dig., Int""l Elec. Devs. Meeting 1993, pages 127-130, describe embodiments of IGFET 30 in which p-type dopant is introduced into channel zone 18 in such a manner that the maximum concentration of the implanted dopant occurs 0.07-0.10 xcexcm below the upper semiconductor surface. Instead of boron, Shahidi et al employs indium, a slow-diffusing species, as the p-type dopant for the implant into channel zone 18. Shahidi also employs indium for the halo pockets. While indium may provide profile steepness and better short-channel behavior, indium is not commonly used in semiconductor manufacturing processes and may cause process implementation difficulties.
Hwang et al, cited above, describes an n-channel IGFET in which a p-type implant is performed relatively deep into the channel zone in order to alleviate punchthrough. The depth of the maximum concentration of the p-type anti-punchthrough implant in this IGFET of Hwang et al appears to occur below the channel surface depletion region. In comparing a halo IGFET to an IGFET having an anti-punchthrough implant but no halo pocket(s), Hwang et al determines that less threshold voltage roll-off occurs in the halo IGFET.
Conventional semiconductor manufacturing processes achieve varying degrees of success in avoiding punchthrough and alleviating threshold voltage roll-off. It is desirable to have an IGFET structure and fabrication technique for overcoming these problems. In so doing, it is desirable to avoid use of semiconductor dopants which are not widely employed in volume-production IC fabrication and which could cause manufacturing difficulties. It is also desirable to have a semiconductor structure in which different IGFETs can readily be provided with different threshold voltages.
The present invention furnishes an insulated-gate field-effect transistor whose doping is controlled to alleviate threshold voltage roll-off and avoid punchthrough at short channel length. The average doping in the channel zone of the present IGFET changes with channel length in such a manner that the variation of threshold voltage with channel length in the short-channel operational regime where threshold voltage roll-off occurs in an otherwise conventional IGFET is considerably less than in the conventional IGFET. The channel length of the present IGFET can thereby be reduced below the normal value at which threshold voltage roll-off occurs without having the magnitude of the threshold voltage drop significantly. Fabrication variations that result in unintended channel length differences do not lead to substantial threshold voltage differences in the present IGFET.
More particularly, the channel zone of the present IGFET is situated in body material of a semiconductor body. The channel zone laterally separates a pair of source/drain zones situated in the semiconductor body along its upper surface. The source/drain zones form pn junctions with the body material. A gate electrode overlies a gate dielectric layer above the channel zone.
The dopant profile of the present IGFET has two important characteristics, one directed primarily towards alleviating short-channel threshold voltage roll-off and the other directed primarily towards alleviating punchthrough. The first characteristic is that the net dopant concentration of the channel zone along the upper semiconductor surface longitudinally reaches a local surface minimum between the source/drain zones. The channel dopant profile along the upper semiconductor surface in the longitudinal direction, i.e., along the IGFET""s channel length, thus typically has at least a half-saddle shape, typically a full saddle shape.
The average value of the channel zone""s net dopant concentration normally increases with decreasing channel length for a given amount of semiconductor dopant (per unit channel width) producing the channel surface dopant profile. By arranging for the average net dopant concentration of the channel zone to vary in this manner, the magnitude of the threshold voltage of the present IGFET increases slowly with decreasing channel length in passing through the value of channel length at which short-channel threshold voltage roll-off starts to occur in an otherwise similar conventional IGFET. Since the magnitude of the threshold voltage of the present IGFET increases with decreasing channel length in this short-channel operational regime rather than decreasing sharply with decreasing channel length, the variation of the threshold voltage with channel length in the short-channel regime is considerably less than in the conventional IGFET. The onset of threshold voltage roll-off in the present IGFET is thereby advantageously shifted to lower channel length.
The second important characteristic of the dopant profile of the present IGFET is that the net dopant concentration of the body material reaches a local subsurface maximum more than 0.1 xcexcm below the upper semiconductor surface but not more than 0.4 xcexcm below the upper semiconductor surface. Also, the local subsurface maximum of the body material""s net dopant concentration occurs below a channel surface depletion region that extends along the upper semiconductor surface into the channel zone. The local subsurface maximum of the body material""s net dopant concentration normally exceeds the local surface minimum of the channel zone""s net dopant concentration. The vertical dopant profile through the local subsurface minimum is therefore of a retrograde nature.
The semiconductor dopant which produces the local subsurface maximum in the body material""s net dopant concentration causes the thicknesses of the body-material portions of the depletion regions along the source/drain zones to be reduced at a given voltage between the source/drain zones. The source/drain zone acting as the drain (at any particular time) is thereby inhibited from punching through to the source/drain zone acting as the source.
A feature of the present invention is that the gate dielectric layer is typically 2-10 nm in thickness. While the gate dielectric layer normally contains atoms of semiconductor material, typically silicon, and atoms of oxygen combined to form semiconductor oxide, typically silicon oxide, atoms of nitrogen may also be incorporated into the gate dielectric layer. That is, the gate dielectric layer may contain semiconductor oxynitride, typically silicon oxynitride.
In a structure containing two implementations of the present IGFET, the channel zones of the two IGFETs can readily be of sufficiently different length that the IGFETs differ significantly in threshold voltage. With the local surface minima in the net dopant concentrations of the channel zones being produced by approximately equal amounts of semiconductor dopant (per unit channel width) as occurs when IGFETs are manufactured under largely identical fabrication process conditions, the shorter channel zone normally has the higher average net dopant concentration. Accordingly, the FET with the shorter channel zone normally has the higher magnitude of threshold voltage.
While two IGFETs with significantly different threshold voltages can be provided in the same structure of the invention by suitably choosing the channel lengths, two such IGFETs can also be provided in different structures. In other words, identical fabrication process conditions can be employed to provide separate structures with IGFETs of significantly different threshold voltage by simply making the channel lengths sufficiently different.
Fabrication of an IGFET in accordance with the invention begins with a semiconductor body having body material of a first conductivity type. First semiconductor dopant, referred to here as the anti-punchthrough (xe2x80x9cAPTxe2x80x9d) dopant, of the first conductivity type is introduced into the body material. This doping step is performed in such a manner that, subsequent to providing an electrically insulated gate electrode above a portion of the body material intended to be a channel zone, the maximum concentration of the APT dopant occurs more than 0.1 xcexcm into the body material but not more than 0.4 xcexcm into the body material. The maximum concentration of the APT dopant also occurs below the location where a channel surface depletion region extends into the channel zone during IGFET operation. The doping characteristic achieved with the APT dopant provides punchthrough protection.
The APT dopant is normally ion implanted into the body material. Since the maximum concentration of the APT dopant occurs below the channel surface depletion region, substantially only part of the xe2x80x9cheadxe2x80x9d (upper portion) of the implant of the APT dopant affects the IGFET""s threshold voltage. Consequently, the threshold voltage can be controlled largely independent of channel length by simply adjusting the implantation energy. As the implantation energy increases, less of the APT dopant accumulates in the channel surface depletion region, thereby causing the magnitude of the threshold voltage to be reduced. The ability to control the threshold voltage by adjusting the implantation energy provides enhanced flexibility over a conventional threshold adjust implant in which adjustment of the implantation dosage is the primary mechanism for controlling the threshold voltage.
Later in the fabrication process after forming the gate electrode, second semiconductor dopant, referred to here as the halo dopant, of the first conductivity type is introduced into at least the intended channel-zone portion of the body material. Also, dopant, referred to here as the source/drain dopant, of a second conductivity type opposite to the first conductivity type is introduced into the semiconductor body to form a pair of source/drain zones laterally separated by the channel zone. These doping operations are performed in a way that enables the concentration of the halo dopant to longitudinally reach a local surface minimum in the channel zone along the upper semiconductor surface. The doping characteristic provided by the halo dopant alleviates short-channel threshold voltage roll-off and assists the APT dopant in providing punchthrough protection.
The halo and source/drain dopants enter the body material by passing through the upper semiconductor surface. A shield formed with at least the gate electrode is preferably utilized to largely prevent the halo and source/drain dopants from passing through the section of the upper semiconductor surface underlying at least the gate electrode. The doping operation with the source/drain dopant may be performed in at least two separate steps so as to form each source/drain zone as a main portion and a more lightly doped extension. The channel zone is terminated by the source/drain extensions along the upper semiconductor surface.
The halo dopant forms one or more pocket portions akin to halo when the halo dopant is introduced into the intended channel-zone portion of the body material using a dopant-blocking shield consisting of at least the gate electrode. Angled ion implantation is preferably employed to introduce the halo dopant into the channel-zone portion of the body material. Specifically, ions of the halo dopant are implanted into the channel-zone portion of the body material at an average tilt angle of at least 15xc2x0 relative to a direction generally perpendicular to the upper semiconductor surface. By using angled ion implantation, the halo dopant can be placed where it yields a large reduction in short-channel threshold voltage roll-off.
An additional feature of the present invention is that each source/drain zone can have a vertically xe2x80x9cgradedxe2x80x9d junction characteristic. That is, in moving upward from the pn junction between a source/drain zone and the adjoining body material, the net dopant concentration in a vertical cross-section through the source/drain zone rises less sharply, on the average, to the maximum value of the net dopant concentration in that vertical cross-section than what would occur if the semiconductor dopant which defines the source/drain zone across that vertical cross-section were ion implanted at largely a single energy. The graded-junction characteristic reduces the junction capacitance, thereby leading to an increase in the IGFET switching speed.
The graded-junction characteristic is attained by configuring each source/drain zone to have a main source/drain portion and a more lightly doped lower source/drain portion which underlies, and is vertically continuous with, the main source/drain portion. In fabricating the present IGFET to have a vertically graded pn junction, first semiconductor of the second conductivity type is introduced into the semiconductor body at a first dosage and to a first average depth (below the upper semiconductor surface). Second semiconductor dopant of the second conductivity type is introduced into the semiconductor body at a second dosage less than the first dosage and to a second average depth greater than the first average depth such that the first dopant of the second conductivity type defines the main source/drain portions while the second dopant of the second conductivity type defines the more lightly doped lower source/drain portions.
More generally, a p-channel IGFET configured in accordance with the invention contains a channel zone situated in a semiconductor body having an upper surface. A gate electrode overlies a gate dielectric layer above the channel zone. The channel zone laterally separates a pair of p-type source/drain zones of the semiconductor body. Each p-type source/drain zone has a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main portion. Consequently, the p-channel IGFET has a graded-junction characteristic.
Fabrication of such a graded junction p-channel IGFET entails providing the gate electrode over the gate dielectric layer above a location for the channel zone in the semiconductor body. First, p-type semiconductor dopant is introduced, typically by ion implanting a species of the first p-type dopant, into the semiconductor body at a first dosage and to a first average depth. Second, p-type semiconductor dopant is introduced, likewise typically by ion implanting a species of the second p-type dopant, into the semiconductor body at a second dosage less than the first dosage and to a second average depth greater than the first average depth. The dopant-introduction steps are controlled so that the first p-type dopant defines the main portions of the source/drain zones, so that the second p-type dopant defines the lower source/drain portions, and so that the lower portions are more lightly doped than, and respectively vertically continuous with, the main portions.
The p-type dopant species, typically a boron-containing compound such as boron difluoride, employed in defining the main portions of the source/drain zones is preferably of greater molecular weight than the p-type dopant species, typically elemental boron, utilized in defining the lower source/drain portions. With boron being an atom of relatively low molecular weight and with the main source/drain portions being shallower than the lower source/drain portions, one reason for this difference in dopant species is that it is difficult to reliably control typical commercially available state-of-the-art ion-implantation equipment at the low implantation energy (e.g., 5 KeV) which would generally be appropriate if elemental boron were the p-type species utilized to define the main source/drain portions. Performing the implantation to define the main source/drain portions with a p-type dopant species, e.g., boron difluoride, of greater molecular weight than the p-type dopant species, e.g., elemental boron, utilized to define the lower source/drain portions thus facilitates accurately forming the graded-junction characteristic.
In short, an IGFET configured and fabricated according to the invention normally has a dopant profile that causes the onset of short-channel threshold voltage roll-off to be shifted to lower channel length than occurs in an otherwise similar conventional IGFET. Punchthrough is substantially alleviated in the present invention. The threshold voltage can be controlled largely independent of channel length by adjusting the energy of implanted ions of dopant utilized to avoid punchthrough. For the same, or substantially the same, fabrication process conditions, IGFETs of significantly different threshold voltage are achieved by simply utilizing appropriately different channel lengths. An IGFET, especially a p-type channel device, configured and fabricated according to the invention, can be provided with a graded-junction characteristic. The invention thus provides a large advance over the prior art.